1. Field of the Invention
The present invention relates generally to the field of semiconductor processing and, more specifically, to thermal annealing during semiconductor device fabrication.
2. Description of the Related Art
Rapid thermal processing (RTP) is a process for annealing substrates during semiconductor fabrication. During this process, thermal radiation is used to rapidly heat a substrate in a controlled environment to a maximum temperature of over nine hundred degrees above room temperature. This maximum temperature is maintained for less than one second to several minutes, depending on the process. The substrate is then cooled to room temperature for further processing. High intensity tungsten or halogen lamps are used as the source of thermal radiation. Conductively coupling the substrate to a heated susceptor provides additional heat.
The semiconductor fabrication process has several applications of RTP. Such applications include thermal oxidation (a substrate is heated in oxygen or a combination of oxygen and hydrogen which causes the silicon substrate to oxidize to form silicon dioxide); high temperature soak anneal (different gas mixtures such as nitrogen, ammonia, or oxygen are used); low temperature soak anneal (typically to anneal wafers deposited with metals); and spike anneal (primarily used in processes where the substrate needs to be exposed to high temperatures for a very short time). During a spike anneal, the substrate is rapidly heated to a maximum temperature sufficient to activate a dopant and cooled rapidly to end the activation process prior to substantial diffusion of the dopant.
A method and apparatus for spike anneal is described in U.S. patent application No. 2003/0183611, published Oct. 2, 2003, which is hereby incorporated by reference herein. During a spike anneal, the substrate is heated using thermal radiation from an array of lamps. Typically, the substrate is heated at a ramp rate of up to 250° C./sec to temperatures greater than 1000° C. The substrate is then cooled by conductively coupling the hot substrate to the cold reflector plate using a blanket of inert gas such as helium gas. This forced cooling facilitates a faster cooling rate, achieving ramp down rates of up to 80° C./sec.
Activating the polysilicon gate electrode without causing dopant diffusion is a major challenge for front end of line (FEOL) processing. A delicate balance exists between enhanced dopant activation and aggregated dopant diffusion. An aggressive activation anneal may lead to high carrier concentration, but the dopant may be driven into the gate dielectric layer or even into the channel region. The balance becomes more difficult to maintain as device makers try to overcome poly-depletion. Poly-depletion is a reduction of activated dopants within the inversion region of a polysilicon layer. Poly-depletion accounts for an increasing fraction of Tox-inv (carrier concentration/poly-depletion) as gate lengths and gate dielectric thicknesses become smaller. For substrate features in the size of 130 nm and 90 nm, conventional thermal processes such as rapid thermal processing (RTP) and spike annealing are the main dopant activation methods. The resulting poly-depletion contributes 4-5 Å to Tox-inv. An additional reduction of 1 Å of the poly-depletion is necessary for a substrate feature with the size of 65 nm. Drive current gain of about 3% is expected with each angstrom of poly-depletion reduction. Conventional thermal processes are not capable of annealing such small substrate features without provoking dopant diffusion. In addition, preventing dopant penetration and use of thermally sensitive high-k materials requires low thermal budget activation anneal.
Laser anneal, which can achieve high dopant activation without driving dopant diffusion, has been developed to meet the requirements for poly-depletion for use in 65 nm features. Laser annealing technology produces transient temperatures such as about 1350° C. near the silicon melting point within a few milliseconds, which results in high dopant activation with little dopant diffusion. This is a particular benefit for a process such as boron activation, since boron diffuses much faster than does phosphorous and arsenic. However, laser anneal temperatures that melt the silicon have been shown to cause polycrystalline grain size growth which may result in device yield loss.
The object of annealing is often a substantially uniform temperature profile across the substrate. This is achieved by controlling a laser, an array of lamps, or other heat sources which uniformly heat the substrate on the front side while a reflective surface on the back side of the substrate uniformly reflects heat back to the substrate. Emissivity measurement and compensation methodology have been used to improve the uniform temperature gradient across the substrate.
However, uniform control of an anneal chamber that also incorporates the use of a laser often does not provide substantially uniform temperature profiles across the diameter of the substrate. Thus, apparatus and methods to improve uniformity remain of interest and there is a need to have a process for doping polycrystalline layers within a feature and annealing and activating the doped polycrystalline with minimal or no dopant diffusion.